The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2019

Filed:

Aug. 07, 2017
Applicant:

Raytheon Company, Waltham, MA (US);

Inventor:

Eric R. Schneider, North Andover, MA (US);

Assignee:

RAYTHEON COMPANY, Waltham, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2016.01); G06F 9/4401 (2018.01); G06F 12/14 (2006.01); G06F 12/1081 (2016.01); G06F 12/1009 (2016.01);
U.S. Cl.
CPC ...
G06F 12/1081 (2013.01); G06F 9/4403 (2013.01); G06F 9/4405 (2013.01); G06F 12/1009 (2013.01); G06F 12/1483 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/65 (2013.01); G06F 2212/657 (2013.01);
Abstract

Aspects are directed to a start-up or recovery method and a central processing unit (CPU) architecture. In one example, the CPU architecture includes read-only memory (ROM) storing instructions addressable by a first range of physical memory addresses, random access memory (RAM), a direct memory access (DMA) engine, the DMA engine controllable to transfer the instructions from the ROM to RAM, the instructions addressable by a second range of physical memory addresses at the RAM, a memory management unit configured to translate a range of virtual addresses to the first range while in ROM, and translate the range of virtual memory addresses to the second range while in RAM, and a CPU to execute a DMA interrupt service routine to update the memory management unit to translate the range of virtual addresses to the second range of physical memory addresses while the DMA engine transfers the instructions to RAM.


Find Patent Forward Citations

Schneider, Eric. (2019). Central processing unit architecture and methods for high availability systems (U.S. Patent No. 10452561). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10452561

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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