The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2019

Filed:

Oct. 05, 2018
Applicant:

Western Digital Technologies, Inc, San Jose, CA (US);

Inventors:

Igor Genshaft, Bat Yam, IL;

Marina Frid, Jerusalem, IL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 12/1018 (2016.01); G06F 12/109 (2016.01); G06F 12/0864 (2016.01); G06F 12/0891 (2016.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1018 (2013.01); G06F 12/0246 (2013.01); G06F 12/0864 (2013.01); G06F 12/0891 (2013.01); G06F 12/109 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/657 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7207 (2013.01);
Abstract

Apparatuses, systems, methods, and computer program products are disclosed for address range mapping for memory devices. A system includes a set of non-volatile memory elements accessible using a set of physical addresses and a controller for the set of non-volatile memory elements. A controller is configured to maintain a hierarchical data structure for mapping logical addresses to a set of physical addresses. A hierarchical data structure comprises a plurality of levels with hashed mappings of ranges of logical addresses at range sizes selected based on a relative position of an associated level within the plurality of levels. A controller is configured to receive an I/O request for data of at least one logical address. A controller is configured to satisfy an I/O request using a hashed mapping having a largest available range size to map at least one logical address of the I/O request to one or more physical addresses.


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