The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2019

Filed:

Apr. 08, 2016
Applicants:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Ati Technologies Ulc, Markham, CA;

Inventors:

Ihab Amer, Markham, CA;

Khaled Mammou, Vancouver, CA;

Haibo Liu, Markham, CA;

Edward Harold, Markham, CA;

Fabio Gulino, Markham, CA;

Samuel Naffziger, Fort Collins, CO (US);

Gabor Sines, Markham, CA;

Lawrence A. Bair, Boxborough, MA (US);

Andy Sung, Markham, CA;

Lei Zhang, Markham, CA;

Assignees:

ADVANCED MICRO DEVICES, INC., Sunnyvale, CA (US);

ATI TECHNOLOGIES ULC, Markham, Ontario, CA;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G11C 11/417 (2006.01); G06F 12/0877 (2016.01); G06F 12/0893 (2016.01); G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0877 (2013.01); G06F 12/0893 (2013.01); G11C 11/417 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/221 (2013.01); G06F 2212/60 (2013.01); G11C 5/148 (2013.01);
Abstract

Systems, apparatuses and methods of adaptively controlling a cache operating voltage are provided that comprise receiving indications of a plurality of cache usage amounts. Each cache usage amount corresponds to an amount of data to be accessed in a cache by one of a plurality of portions of a data processing application. The plurality of cache usage amounts are determining based on the received indications of the plurality of cache usage amounts. A voltage level applied to the cache is adaptively controlled based on one or more of the plurality of determined cache usage amounts. Memory access to the cache is controlled to be directed to a non-failing portion of the cache at the applied voltage level.


Find Patent Forward Citations

Loading…