The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2019

Filed:

Dec. 20, 2017
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventor:

Michael K. Ciraula, Fort Collins, CO (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/22 (2006.01); H03M 13/01 (2006.01); G06F 11/10 (2006.01); G06F 11/34 (2006.01); G11C 29/12 (2006.01); G06F 11/07 (2006.01); G11C 29/10 (2006.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 11/2215 (2013.01); G06F 9/30029 (2013.01); G06F 11/073 (2013.01); G06F 11/0745 (2013.01); G06F 11/0793 (2013.01); G06F 11/1068 (2013.01); G06F 11/3409 (2013.01); G11C 29/10 (2013.01); H03M 13/015 (2013.01); G11C 2029/1202 (2013.01);
Abstract

A memory system includes a non-volatile memory unit, a content-addressable memory unit coupled to the non-volatile memory unit, and an error injection logic unit coupled to the non-volatile memory unit and the content addressable memory unit. The non-volatile memory unit is programmed to allow a first error injection onto a first data word using the error injection logic unit. The error injection logic in combination with the content addressable memory unit replaces a bit cell in the memory system. The memory system performs an evaluation of various error detection and correction techniques.


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