The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2019

Filed:

Sep. 13, 2017
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventor:

Naoki Shimizu, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G11C 13/00 (2006.01); G11C 11/16 (2006.01); G11C 29/52 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G06F 11/1048 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/1693 (2013.01); G11C 11/1697 (2013.01); G11C 13/004 (2013.01); G11C 13/0023 (2013.01); G11C 13/0038 (2013.01); G11C 13/0061 (2013.01); G11C 13/0069 (2013.01); G11C 29/52 (2013.01); G11C 2013/0076 (2013.01); G11C 2029/0411 (2013.01);
Abstract

According to one embodiment, a memory system includes a resistance change type memory including a memory cell configured to hold first data and an ECC circuit configured to detect and to correct an error in the first data; and a controller configured to control an operation of the resistance change type memory. In a read operation for the memory, when the first data from the memory cell includes an error, the memory transmits second data in which the error is corrected and a first signal to the controller. The controller transmits a control signal and a write command to the memory based on the first signal. The memory writes the second data to the memory cell based on the control signal and the write command.


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