The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2019

Filed:

May. 10, 2017
Applicant:

Ambarella, Inc., Santa Clara, CA (US);

Inventor:

Peter Verplaetse, Redwood City, CA (US);

Assignee:

Ambarella, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/50 (2006.01); G06F 9/48 (2006.01); G06F 16/901 (2019.01);
U.S. Cl.
CPC ...
G06F 9/5044 (2013.01); G06F 9/4881 (2013.01); G06F 9/5038 (2013.01); G06F 16/9024 (2019.01);
Abstract

An apparatus includes a plurality of hardware engines and a scheduler circuit. The hardware engines may be configured to process a plurality of vectors using a plurality of operators. The scheduler circuit may be configured to (i) parse a directed acyclic graph into one or more of the operators, (ii) track a plurality of unscheduled operators that have not been allocated to the hardware engines, (iii) track a plurality of statuses of the hardware engines and (iv) allocate at least one of the unscheduled operators to at least one of the hardware engines based on the statuses. The at least one unscheduled operator may be processed in the at least one hardware engine. The scheduler circuit may be implemented solely in hardware.


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