The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 2019
Filed:
Oct. 27, 2016
Nvidia Corporation, Santa Clara, CA (US);
Milind Sonawane, San Jose, CA (US);
Amit Sanghani, San Jose, CA (US);
Shantanu Sarangi, Saratoga, CA (US);
Jonathon E. Colburn, Ben Lomond, CA (US);
Bala Tarun Nelapatla, Santa Clara, CA (US);
Sailendra Chadalavda, Milpitas, CA (US);
Rajendra Kumar Reddy.S, Bangalore, IN;
Mahmut Yilmaz, Los Altos Hills, CA (US);
Pavan Kumar Datla Jagannadha, Santa Clara, CA (US);
Nvidia Corporation, Santa Clara, CA (US);
Abstract
A method for testing. An external clock frequency is generated. Test data is supplied over a plurality of SSI connections clocked at the external clock frequency, wherein the test data is designed for testing a logic block. A DSTA module is configured for the logic block that is integrated within a chip to a bandwidth ratio, wherein the bandwidth ratio defines the plurality of SSI connections and a plurality of PSI connections of the chip. The external clock frequency is divided down using the bandwidth ratio to generate an internal clock frequency, wherein the bandwidth ratio defines the external clock frequency and the internal clock frequency. The test data is scanned over the plurality of PSI connections clocked at the internal clock frequency according to the bandwidth ratio, wherein the plurality of PSI connections is configured for inputting the test data to the plurality of scan chains.