The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2019

Filed:

Nov. 13, 2017
Applicant:

Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;

Inventors:

Tom Hanley, Edinburgh, GB;

Timothy John Brosnihan, Austin, TX (US);

Euan James Boyd, Edinburgh, GB;

Assignee:

Cirrus Logic, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B81B 3/00 (2006.01); B81C 1/00 (2006.01); H04R 9/08 (2006.01); H04R 19/04 (2006.01); H04R 19/00 (2006.01); H04R 31/00 (2006.01);
U.S. Cl.
CPC ...
B81B 3/001 (2013.01); B81C 1/00984 (2013.01); H04R 9/08 (2013.01); H04R 19/04 (2013.01); B81B 2201/0257 (2013.01); B81B 2203/033 (2013.01); B81B 2203/0376 (2013.01); B81B 2207/012 (2013.01); B81C 2201/115 (2013.01); H04R 19/005 (2013.01); H04R 31/006 (2013.01); H04R 2201/003 (2013.01);
Abstract

The application describes a MEMS transducer comprising a substrate having a cavity. The transducer exhibits a membrane layer supported relative to the substrate to define a flexible membrane. An upper surface of the substrate comprises an overlap region between the edge of the cavity and a perimeter of the flexible membrane where the membrane overlies the upper surface of the substrate. At least one portion of the overlap region of the upper surface of the substrate is provided with a plurality of recesses. The recesses are defined so as to extend from the edge of the cavity towards the perimeter of the flexible membrane.


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