The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2019

Filed:

Sep. 13, 2017
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventors:

Paul Hanham, Wiltshire, GB;

David Symons, Oxon, GB;

Francesco Giorgio, Oxon, GB;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/11 (2006.01); G06F 3/06 (2006.01); G06F 11/10 (2006.01); H03M 13/29 (2006.01); H03M 13/15 (2006.01);
U.S. Cl.
CPC ...
H03M 13/1108 (2013.01); G06F 3/065 (2013.01); G06F 3/0619 (2013.01); G06F 3/0679 (2013.01); G06F 11/1012 (2013.01); H03M 13/2906 (2013.01); H03M 13/152 (2013.01);
Abstract

A solid state storage device comprises a non-volatile memory controller configured to store data in a non-volatile memory, wherein the stored data is encoded using a first error-correcting code and a second Low Density Parity Check (LDPC) code. The non-volatile memory controller includes a hard-decision LDPC decoder to decode encoded data received from the non-volatile memory and provide a decoded data output. The hard-decision LDPC decoder selects a voting scheme at each iteration in a sequence of iterations of decoding to determine when to implement bit flipping at a variable node amongst a plurality of check nodes, each of the plurality of check nodes connected to a plurality of variable nodes.


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