The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 2019
Filed:
Oct. 27, 2016
Applicant:
Andapt, Inc., San Jose, CA (US);
Inventors:
Kapil Shankar, Saratoga, CA (US);
Thomas Chan, Saratoga, CA (US);
Patrick J. Crotty, San Jose, CA (US);
John Birkner, Woodside, CA (US);
Assignee:
AnDAPT, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2006.01); G06F 1/28 (2006.01); G05F 1/66 (2006.01); H02M 3/158 (2006.01); H03K 19/0175 (2006.01);
U.S. Cl.
CPC ...
H03K 19/17772 (2013.01); G05F 1/66 (2013.01); G06F 1/28 (2013.01); H02M 3/158 (2013.01); H03K 19/017509 (2013.01); H03K 19/1776 (2013.01); H03K 19/17744 (2013.01); H02M 3/1588 (2013.01); Y02B 70/1466 (2013.01);
Abstract
A power management integrated circuit (PMIC) includes: a plurality of high voltage power field effect transistors (FETs); and a programmable fabric configured to programmably connect one or more of the plurality of high voltage power FETs to provide one or more high power voltage outputs. The plurality of high voltage power FETs and the programmable fabric are integrated in a single chip.