The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2019

Filed:

Dec. 02, 2015
Applicant:

Telefonaktiebolaget Lm Ericsson (Publ), Stockholm, SE;

Inventor:

Reza Bagger, Järfälla, SE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/356 (2006.01); H03K 3/3562 (2006.01); H03K 21/10 (2006.01); H03K 23/42 (2006.01); H03K 19/20 (2006.01); H04B 1/40 (2015.01); H03K 5/15 (2006.01); H03K 3/37 (2006.01); H03K 23/48 (2006.01);
U.S. Cl.
CPC ...
H03K 3/356104 (2013.01); H03K 3/356 (2013.01); H03K 3/35625 (2013.01); H03K 3/356139 (2013.01); H03K 3/37 (2013.01); H03K 5/15066 (2013.01); H03K 19/20 (2013.01); H03K 21/10 (2013.01); H03K 23/425 (2013.01); H04B 1/40 (2013.01); H03K 23/483 (2013.01);
Abstract

The present invention relates to a combiner latch circuit for generation of one phase differential signal pair or two phase differential signal pairs. The combiner latch circuit comprises an input circuit configured to select a state of the output circuit from a group of: a fourth state comprising the differential output X=1, Y=0, a fifth state comprising the differential output X=0, Y=1. The input circuit is further configured to select the fourth state if the input A=0 and the input B=1 and the clock input encounter a leading edge from 0 to 1 and the output circuit is in the fifth state, and select the fifth state if the input A=1 and the input B=0 and the clock input encounter a leading edge from 0 to 1 and the output circuit is in the fourth state.


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