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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10446677 B1

PDFFull Text
Date of Patent:
Oct. 15, 2019

Filed:

Mar. 16, 2018

Semiconductor structures and method for fabricating the same

Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventor:

Francois Hebert, Hsinchu, TW;

Assignee:

VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION, Hsinchu, TW;

Attorney:

Birch, Stewart, Kolasch & Birch, LLP

Primary Examiner:

Didarul A Mazumder

Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/778 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 23/373 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 21/02 (2006.01); H01L 21/762 (2006.01); H01L 21/84 (2006.01); H01L 21/306 (2006.01); H01L 21/265 (2006.01); H01L 27/06 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7787 (2013.01); H01L 21/0242 (2013.01); H01L 21/0254 (2013.01); H01L 21/02376 (2013.01); H01L 21/02378 (2013.01); H01L 21/02458 (2013.01); H01L 21/02488 (2013.01); H01L 21/02505 (2013.01); H01L 21/2654 (2013.01); H01L 21/30612 (2013.01); H01L 21/76224 (2013.01); H01L 21/84 (2013.01); H01L 23/3731 (2013.01); H01L 23/3732 (2013.01); H01L 23/3738 (2013.01); H01L 27/0605 (2013.01); H01L 27/1203 (2013.01); H01L 29/0649 (2013.01); H01L 29/0843 (2013.01); H01L 29/1075 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/66462 (2013.01);
Abstract

A semiconductor structure is provided. The semiconductor structure includes an insulating substrate including a first region and a second region; an engineered layer surrounding the insulating substrate; a nucleation layer formed on the engineered layer; a buffer layer formed on the nucleation layer; a first epitaxial layer formed on the buffer layer; a second epitaxial layer formed on the first epitaxial layer; an isolation structure at least formed in the second epitaxial layer, the first epitaxial layer and the nucleation layer, and located between the first region and the second region; a first gate, a first source and a first drain formed on the second epitaxial layer within the first region; and a second gate, a second source, and a second drain formed on the second epitaxial layer within the second region.

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