The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2019

Filed:

Jan. 25, 2017
Applicant:

Littelfuse, Inc., Chicago, IL (US);

Inventor:

Kyoung Wook Seok, Milpitas, CA (US);

Assignee:

LITTELFUSE, INC., Chicago, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/761 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0634 (2013.01); H01L 21/4853 (2013.01); H01L 21/565 (2013.01); H01L 21/761 (2013.01); H01L 23/3114 (2013.01); H01L 23/49562 (2013.01); H01L 23/49568 (2013.01); H01L 29/0619 (2013.01); H01L 29/0623 (2013.01); H01L 29/0692 (2013.01); H01L 29/408 (2013.01); H01L 29/66712 (2013.01); H01L 29/7811 (2013.01); H01L 29/402 (2013.01);
Abstract

A Super Junction Field Effect Transistor (FET) device includes a charge compensation region disposed on a substrate of semiconductor material. The charge compensation region includes a set of strip-shaped P− type columns, a floating ring-shaped P− type column that surrounds the set of strip-shaped P− type columns, and a set of ring-shaped P− type columns that surrounds the floating ring-shaped P− type column. A source metal is disposed above portions of the charge compensation region. The source metal contacts each of the strip-shaped P− type columns and each of the ring-shaped P− type columns. An oxide is disposed between the floating P− type column and the source metal such that the floating P− type column is electrically isolated from the source metal. The device exhibits a breakdown voltage that is 0.2% greater than if the floating P− type column were to contact the source metal.


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