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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10446568 B1

PDFFull Text
Date of Patent:
Oct. 15, 2019

Filed:

Nov. 13, 2018

Semiconductor memory and semiconductor memory manufacturing method

Applicant:

Lapis Semiconductor Co., Ltd., Kanagawa, JP;

Inventor:

Nobukazu Murata, Kanagawa, JP;

Assignee:

LAPIS SEMICONDUCTOR CO., LTD., Yokohama, JP;

Attorney:

Volentine, Whitt & Francos, PLLC

Primary Examiner:

Theresa T Doan

Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/76 (2006.01); H01L 27/11558 (2017.01); H01L 21/3215 (2006.01); H01L 27/11521 (2017.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 29/94 (2006.01); H01L 27/11524 (2017.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11558 (2013.01); H01L 21/32155 (2013.01); H01L 27/11521 (2013.01); H01L 27/11524 (2013.01); H01L 29/0684 (2013.01); H01L 29/1095 (2013.01); H01L 29/66825 (2013.01); H01L 29/7883 (2013.01); H01L 29/94 (2013.01); H01L 21/02164 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01);
Abstract

The present disclosure provides a semiconductor memory including a first capacitor, a second capacitor, and a transistor. The first capacitor includes a first conductive layer provided on a surface of an n-well, n-type diffusion layers provided in a surface layer portion of the n-well, and a p-type diffusion layer provided in the surface layer portion of the n-well so as to be adjacent to the first conductive layer and separated from the n-type diffusion layers. The second capacitor includes a second conductive layer provided on a surface of an n-well, n-type diffusion layers provided in a surface layer portion of the n-well, and a p-type diffusion layer provided in the surface layer portion of the n-well so as to be adjacent to the second conductive layer and separated from the n-type diffusion layers.

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