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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10446537 B1

PDFFull Text
Date of Patent:
Oct. 15, 2019

Filed:

Dec. 07, 2017

Electrostatic discharge devices

Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Gianluca Boselli, Plano, TX (US);

Muhammad Yusuf Ali, Allen, TX (US);

Assignee:

TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);

Attorneys:

Jacqueline J. Garner

Charles A. Brill

Frank D. Cimino

Primary Examiner:

Sophia T Nguyen

Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 23/60 (2006.01); H02H 9/04 (2006.01); H01L 27/24 (2006.01); H01L 29/06 (2006.01); H01L 27/06 (2006.01); H01L 27/102 (2006.01); H01L 23/62 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0248 (2013.01); H01L 23/60 (2013.01); H01L 23/62 (2013.01); H01L 27/0229 (2013.01); H01L 27/0262 (2013.01); H01L 27/067 (2013.01); H01L 27/0682 (2013.01); H01L 27/1022 (2013.01); H01L 27/2409 (2013.01); H01L 29/0649 (2013.01); H02H 9/043 (2013.01); H02H 9/046 (2013.01); H01L 27/0255 (2013.01); H01L 27/0288 (2013.01); H01L 27/0292 (2013.01); H01L 27/0296 (2013.01);
Abstract

In accordance with at least one embodiment, an ESD device comprises: a semiconductor; a pad; a ground rail; a p-well formed in the semiconductor; a first p-type region formed in the p-well and electrically coupled to the ground rail; a first n-type region formed in the p-well and electrically coupled to the pad; a second n-type region formed in the p-well and electrically coupled to the ground rail; an n-well formed in the semiconductor; a first n-type region formed in the n-well; a first p-type region formed in the n-well and electrically coupled to the pad; and a second p-type region formed in the n-well and electrically coupled to the first n-type region formed in the n-well.

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