The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2019

Filed:

Feb. 07, 2017
Applicant:

Tela Innovations, Inc., Los Gatos, CA (US);

Inventor:

Scott T. Becker, Scotts Valley, CA (US);

Assignee:

Tela Innovations, Inc., Los Gatos, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 21/302 (2006.01); H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); G06F 17/5072 (2013.01); H01L 27/088 (2013.01); H01L 27/092 (2013.01); H01L 27/0924 (2013.01); H01L 29/785 (2013.01); G06F 17/5068 (2013.01); G06F 2217/06 (2013.01); G06F 2217/12 (2013.01); H01L 21/302 (2013.01); H01L 21/845 (2013.01); Y02P 90/265 (2015.11);
Abstract

A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the first direction. A number of gate level structures are defined to extend in a conformal manner over some of the number of linear-shaped diffusion fins. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins extend in a second direction that is substantially perpendicular to the first direction. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins form gate electrodes of a corresponding transistor. The diffusion fins and gate level structures can be placed in accordance with a diffusion fin virtual grate and a gate level virtual grate, respectively.


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