The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2019

Filed:

Sep. 26, 2014
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Takafumi Betsui, Tokyo, JP;

Motoo Suwa, Tokyo, JP;

Assignee:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2006.01); H01L 21/66 (2006.01); H01L 23/00 (2006.01); H01L 25/16 (2006.01); H01L 25/00 (2006.01); G11C 5/02 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2006.01); H01L 23/50 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); G11C 5/025 (2013.01); H01L 22/14 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 24/81 (2013.01); H01L 25/16 (2013.01); H01L 25/50 (2013.01); H01L 23/49816 (2013.01); H01L 23/50 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 25/0655 (2013.01); H01L 2224/13007 (2013.01); H01L 2224/16014 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/1713 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/15174 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19102 (2013.01);
Abstract

An electronic device includes a first wiring substrate and a semiconductor device mounted on the first wiring substrate. A plurality of first semiconductor chips and a second semiconductor chip which controls each of the plurality of first semiconductor chips are mounted side by side on a second wiring substrate of the semiconductor device. Further, the plurality of first semiconductor chips are mounted between a first substrate side of the wiring substrate and an extension line of a first chip side of the second semiconductor chip. Furthermore, the first wiring substrate includes a first power line which supplies a first power potential to each of the plurality of first semiconductor chips and a second power line which supplies a second power potential to the second semiconductor chip and has a width larger than that of the first power line. Also, the second power line intersects the first substrate side of the second wiring substrate and extends from a side of the first substrate side of the second wiring substrate toward the second semiconductor chip when seen in a plan view.


Find Patent Forward Citations

Loading…