The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2019

Filed:

Aug. 22, 2017
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Sheng-Mou Lin, Hsin-Chu, TW;

Chih-Chun Hsu, Hsin-Chu, TW;

Wen-Chou Wu, Hsin-Chu, TW;

Assignee:

MEDIATEK INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/66 (2006.01); H01L 23/64 (2006.01); H01L 23/552 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
H01L 23/66 (2013.01); H01L 23/552 (2013.01); H01L 23/645 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2223/6605 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06537 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06572 (2013.01);
Abstract

A semiconductor package structure is provided. The semiconductor package structure includes a package substrate. An integrated circuit (IC) die having a radio frequency (RF) circuit and a memory die are stacked over the package substrate. The memory die entirely covers a first surface portion of the package substrate to define a second surface portion of the package substrate exposed from the memory die, and the IC die partially covers the first surface portion and the second surface portion of the package substrate. The RF circuit includes a first sensitive device region corresponding to the second surface portion of the package substrate and a second sensitive device region corresponding to the first surface portion of the package substrate and offsetting a memory input/output (I/O) electrical path of the memory die, as viewed from a top-view perspective.


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