The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2019

Filed:

Nov. 15, 2017
Applicant:

AU Optronics Corporation, Hsin-chu, TW;

Inventors:

Cheng-Chiu Pai, Hsin-chu, TW;

Ming-Hung Chuang, Hsin-chu, TW;

Assignee:

AU OPTRONICS CORPORATION, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 19/00 (2006.01); G11C 19/28 (2006.01); G09G 3/00 (2006.01); H03K 19/017 (2006.01); G09G 3/20 (2006.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G11C 19/28 (2013.01); G09G 3/003 (2013.01); G09G 3/20 (2013.01); H03K 19/01728 (2013.01); G09G 3/3677 (2013.01); G09G 2300/0408 (2013.01); G09G 2310/0286 (2013.01); G09G 2320/0214 (2013.01); G09G 2330/025 (2013.01); G09G 2330/04 (2013.01);
Abstract

A shift register includes a first switch and a second switch coupled to a first node, a pull-down circuit selectively connecting the first node to a voltage end according to a potential of a second node, a control circuit, and an input stage circuit which may receive a previous-stage shift register output signal, a next-stage shift register output signal, and at least one scanning order logic signal. The first switch receives clock signals. A first output end of the input stage circuit outputs the previous-stage shift register output signal or the next-stage shift register output signal to a control end of the second switch based on the scanning order logic signal. The previous-stage shift register output signal or the next-stage shift register output signal triggers a second output end of the input stage circuit to output the scanning order logic signal to an input end of the control circuit.


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