The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2019

Filed:

Feb. 28, 2018
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventor:

Hiroaki Maekawa, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01); H01L 27/22 (2006.01); H01L 43/08 (2006.01); H01L 25/065 (2006.01); G11C 11/00 (2006.01); G11C 13/00 (2006.01); H01L 43/10 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1675 (2013.01); G11C 11/005 (2013.01); G11C 11/161 (2013.01); G11C 11/1673 (2013.01); G11C 11/1693 (2013.01); G11C 13/0033 (2013.01); G11C 13/0035 (2013.01); G11C 13/0061 (2013.01); G11C 13/0069 (2013.01); H01L 25/0657 (2013.01); H01L 27/228 (2013.01); H01L 43/08 (2013.01); G11C 13/004 (2013.01); H01L 43/10 (2013.01);
Abstract

A semiconductor storage device includes a plurality of first memory elements in a first region and a plurality of second memory elements in a second region. The second memory elements each have a physical volume that is greater than a physical volume of the first memory elements. A controller is configured to first write data to the plurality of first memory elements and then transfer the data written to plurality of first memory elements to the plurality of second memory elements when at least one of an elapsed time since initial writing or a data reading frequency exceeds a threshold value. In general, the first memory elements and the second memory elements are variable resistance elements.


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