The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 2019
Filed:
Nov. 20, 2017
Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;
Kumiko Teramae, Setagaya, JP;
Hikoyuki Kawata, Kawasaki, JP;
Takashi Fukuda, Machida, JP;
Megumi Tanaka, Kawasaki, JP;
FUJITSU LIMITED, Kawasaki, JP;
Abstract
A via model generation method includes: acquiring via arrangement information including a hole diameter of a via formed in a board including a plurality of wiring layers, a clearance distance between a ground conductor formed in one wiring layer of the plurality of wiring layers and the via, and a ground via distance between the via and a ground via coupled to the ground conductor; acquiring board information including a relative dielectric constant of the board; calculating a capacitance component of the via by a first electromagnetic field analysis using the hole diameter of the via, the clearance distance, and the relative dielectric constant of the board; calculating an inductance component of the via by a second electromagnetic field analysis using the hole diameter of the via, the ground via distance, and the relative dielectric constant of the board; and generating a via model including the capacitance and inductance components.