The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2019

Filed:

Jun. 14, 2017
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventor:

Henri Fraisse, Sunnyvale, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5077 (2013.01); G06F 17/504 (2013.01); G06F 17/5031 (2013.01); G06F 17/5054 (2013.01); G06F 17/5068 (2013.01); G06F 17/5081 (2013.01); G06F 2217/06 (2013.01); G06F 2217/84 (2013.01);
Abstract

Routing a circuit design for implementation within an integrated circuit can include determining a set of candidate paths from available paths of the integrated circuit for connecting source-sink pairs of the circuit design, wherein the set of candidate paths is initially a subset of the available paths, and generating, using a processor, an expression having a plurality of variables expressed as a conjunction of routing constraints representing legal routes of the source-sink pairs using only the candidate paths. A routing result for the circuit design can be determined by initiating execution of a SAT solver on the expression using the processor.


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