The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2019

Filed:

Sep. 29, 2017
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Chongqing Boe Optoelectronics Technology Co., Ltd., Chongqing, CN;

Inventors:

Xiaoyuan Wang, Beijing, CN;

Yan Fang, Beijing, CN;

Kui Zhang, Beijing, CN;

Zhicai Xu, Beijing, CN;

Ming Deng, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1345 (2006.01); H01L 27/12 (2006.01); G02F 1/1333 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01);
U.S. Cl.
CPC ...
G02F 1/13458 (2013.01); G02F 1/13452 (2013.01); G02F 1/133345 (2013.01); H01L 27/124 (2013.01); H01L 27/1214 (2013.01); H01L 27/1248 (2013.01); H01L 27/1259 (2013.01); H01L 27/1288 (2013.01); G02F 1/1368 (2013.01); G02F 2001/133357 (2013.01); G02F 2001/136222 (2013.01); G02F 2001/136236 (2013.01);
Abstract

A display substrate and a manufacturing method thereof, and a display device are provided. The manufacturing method of the display substrate includes: forming an insulation layer on a base substrate, the base substrate including a display area and a peripheral area; and forming a planarization film on the insulation layer; performing a patterning process to the planarization film to form a planarization layer with a first thickness in the display area, a planarization layer with a second thickness in the peripheral area, and a first via hole in the planarization layer with the second thickness, the second thickness being less than the first thickness, and performing an etching process on the peripheral area to thin or remove the planarization layer is with the second thickness, and forming a second via hole corresponding to the first via hole in the insulation layer.


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