The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Jun. 19, 2015
Applicant:

Zf Friedrichshafen Ag, Friedrichshafen, DE;

Inventors:

Thomas Preuschl, Sinzing, DE;

Josef Loibl, Bad Abbach, DE;

Assignee:

ZF Friedrichshafen AG, Friedrichshafen, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 5/00 (2006.01); H05K 1/11 (2006.01); H05K 3/28 (2006.01); H05K 3/06 (2006.01); H05K 3/46 (2006.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H05K 5/0082 (2013.01); H05K 1/11 (2013.01); H05K 3/06 (2013.01); H05K 3/282 (2013.01); H05K 3/4644 (2013.01); H05K 5/0017 (2013.01); H05K 1/181 (2013.01); H05K 1/185 (2013.01); H05K 2201/0154 (2013.01); H05K 2203/0759 (2013.01);
Abstract

The present disclosure relates to an electronic transmission controller, with a housing, a printed circuit board assembly, and at least one electronic module mounted on the printed circuit board assembly. The printed circuit board assembly may include a first region extending inside the housing, the first region being sealed from an external fluid. The printed circuit board assembly may include a second region extending outside the housing. The printed circuit board assembly may include a plurality of electrically conductive conductor path layers which are electrically insulated against one another by dielectric layers. An outer layer made of a fluid resistant and electrically insulating material may be applied to at least one outer electrically conductive conductor path layer of the plurality of conductive path layers at a location of the second region of the printed circuit board assembly.


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