The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10440826 B1

Date of Patent:

Oct. 08, 2019

Filed:

Sep. 04, 2017

Semiconductor device

Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventor:

Daisuke Kimura, Yokohama Kanagawa, JP;

Assignee:

TOSHIBA MEMORY CORPORATION, Tokyo, JP;

Attorney:

Kim & Stewart LLP

Primary Examiner:

Binh B Tran

Int. Cl.

CPC ...

H05K 5/00 (2006.01); H05K 1/18 (2006.01); H05K 1/11 (2006.01); H01L 25/18 (2006.01); H01L 25/065 (2006.01); H05K 3/34 (2006.01); H05K 7/00 (2006.01); H01L 23/00 (2006.01); H05K 3/30 (2006.01);

U.S. Cl.

CPC ...

H05K 1/181 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H05K 1/111 (2013.01); H05K 1/117 (2013.01); H05K 3/3436 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/48106 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06586 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1443 (2013.01); H01L 2924/14511 (2013.01); H05K 3/305 (2013.01); H05K 2201/10159 (2013.01); H05K 2201/10522 (2013.01); H05K 2201/10719 (2013.01); H05K 2201/10734 (2013.01);

Abstract

A semiconductor device includes a mounting substrate including an interface, which is connectable with a host, a surface-mounted component mounted on the mounting substrate and having first and second electrode groups, a first solder portion that is positioned between a first electrode in the first electrode group and the mounting substrate to electrically connect the first electrode and the mounting substrate, and a second solder portion that is positioned between a second electrode in the second electrode group and the mounting substrate to electrically connect the second electrode and the mounting substrate. The second solder portion has a larger contact area with the mounting substrate than the first solder portion. The second solder portion is positioned between at least one additional second electrode in the second electrode group to electrically connect the at least one additional second electrode and the mounting substrate.

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