The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Sep. 01, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Joonho Baek, Yongin-si, KR;

Hanjoon Kim, Namyangju-si, KR;

Jeonguk Kang, Bucheon-si, KR;

Dong-Uk Kim, Seoul, KR;

Seungjun Yang, Hwaseong-si, KR;

DuckJoo Lee, Suwon-si, KR;

JinHo Yi, Suwon-si, KR;

Yong-Taek Jeong, Hwaseong-si, KR;

Sangyeun Cho, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/16 (2006.01); H04L 29/08 (2006.01); G06F 12/02 (2006.01); G06F 9/50 (2006.01); H04L 29/06 (2006.01);
U.S. Cl.
CPC ...
H04L 67/1097 (2013.01); G06F 9/5016 (2013.01); G06F 9/5083 (2013.01); G06F 12/023 (2013.01); G06F 12/0253 (2013.01); H04L 67/1002 (2013.01); H04L 67/1076 (2013.01); H04L 69/16 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/154 (2013.01);
Abstract

A server device includes a plurality of interface circuits configured to connect with a network, and perform format conversion between network packets and data chunks, the network packets being packets communicated with the network, the data chunks complying with an internal format; a plurality of memory modules operating independently of each other; and a switch circuit connected between the plurality of interface circuits and the plurality of memory modules, the switch circuit being configured to select at least one memory module from among the plurality of memory modules based on an attribute of a first data chunk transmitted from the plurality of interface circuits and, send the first data chunk to the selected memory module, wherein the selected at least one memory module is configured to, decode the first data chunk, and perform a read or write operation associated with the first data chunk based on the decoding result.


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