The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Jun. 11, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Bohdan Karpinskyy, Suwon-si, KR;

Dae-hyeon Kim, Suwon-si, KR;

Mi-jung Noh, Yongin-si, KR;

Sang-wook Park, Hwaseong-si, KR;

Yong-ki Lee, Yongin-si, KR;

Yun-hyeok Choi, Hwaseong-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); H04L 9/08 (2006.01); G06F 7/58 (2006.01); H03K 19/003 (2006.01); H01L 23/00 (2006.01); H04L 9/32 (2006.01);
U.S. Cl.
CPC ...
H03K 19/003 (2013.01); H01L 23/576 (2013.01); H04L 9/0866 (2013.01); H04L 9/0869 (2013.01); G06F 7/588 (2013.01); H04L 9/3278 (2013.01);
Abstract

An integrated circuit for a physically unclonable function (PUF) includes first and second PUF cells and a combination circuit. The first and second PUF cells respectively output first and second cell signals having unique levels based on a threshold level of a logic gate. The combination circuit includes a first stage that generates a first combination signal based on the first and second cell signals. The first and second PUF cells respectively include first and second logic gates to respectively output the first and second cell signals. The combination circuit includes a third logic gate that receives the first and second cell signals and outputs the first combination signal. The third logic gate has a same structure as each of the first and second logic gates.


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