The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Apr. 13, 2018
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Guolei Yu, Singapore, SG;

Ajay Kumar Kosaraju, Singapore, SG;

Charles Tuten, Scottsdale, AZ (US);

Marko Koski, Chandler, AZ (US);

Aniruddha Bashar, Chandler, AZ (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/017 (2006.01); H03K 3/023 (2006.01); H03H 7/06 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
H03K 3/017 (2013.01); H03K 3/023 (2013.01); H03H 7/06 (2013.01); H03K 19/20 (2013.01);
Abstract

The present disclosure provides a duty locked loop circuit that includes a switch network including a first electronic switch device controlled by a first control signal that is based on a first input signal and a second electronic switch device controlled by a second control signal that is based on a second input signal. The duty locked loop circuit includes an integrator circuit electrically connected to the switch network. The integrator circuit is configured to generate an output voltage proportional to an integral of a difference between a first duty cycle of the first input signal and a second duty cycle of the second input signal. The duty locked loop circuit includes an output circuit configured to generate an output signal having an output duty cycle that is based on the output voltage.


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