The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2019
Filed:
Oct. 15, 2018
Applicant:
Socionext Inc., Kanagawa, JP;
Inventor:
Masahisa Iida, Yokohama, JP;
Assignee:
SOCIONEXT INC., Kanagawa, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01); H03K 3/012 (2006.01); H03K 17/687 (2006.01); H03K 19/0185 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
H03K 3/012 (2013.01); H03K 17/687 (2013.01); H03K 19/018521 (2013.01); H03K 19/20 (2013.01); H03K 2217/0081 (2013.01);
Abstract
In order to reduce a signal propagation delay when an input signal falls, an NMOS transistor (M) is connected between an input terminal () receiving a signal having an amplitude of 3.3 V and an input of an inverter (INV). A first PMOS transistor (M) having a low drive capability and a second PMOS transistor (M) having a high drive capability are connected in parallel between a power supply terminal (VDD) supplying 1.8 V and a gate of the NMOS transistor (M). A gate of the first PMOS transistor (M) is connected to the input of the inverter (INV). A gate of the second PMOS transistor (M) is connected to an output of the inverter (INV).