The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Mar. 14, 2017
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Peter Christiaans, Mountain View, CA (US);

Robert Glenn Crosby, II, Livermore, CA (US);

Fu Chun Zhan, Shanghai, CN;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 15/16 (2006.01); H02M 7/219 (2006.01); G01R 19/00 (2006.01); H02J 7/00 (2006.01); H02J 7/02 (2016.01); H02J 7/04 (2006.01); H02M 1/00 (2006.01);
U.S. Cl.
CPC ...
H02M 7/219 (2013.01); G01R 15/16 (2013.01); G01R 19/0092 (2013.01); H02J 7/0047 (2013.01); H02J 7/027 (2013.01); H02J 7/045 (2013.01); H02M 2001/0009 (2013.01); H02M 2007/2195 (2013.01); Y02B 70/1408 (2013.01);
Abstract

In an example embodiment, an apparatus includes a bridge rectifier circuit having branches between the AC and DC nodes formed by a set of transistors. A load current measurement circuit includes a current-controlled current source coupled to the bridge rectifier circuit. The current control current source is configured to generate a mirrored current that is a scaled version of a current through at least one of the set of transistors. A current integration circuit is configured to integrate the mirrored current by charging a capacitor with the scaled current in a first mode and discharging the capacitor in a second mode. A sample and hold circuit is configured to set an output node to a voltage equal to a voltage stored by the capacitor in response to the current integration circuit entering the second mode and prior to the discharge of the capacitor.


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