The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Mar. 11, 2016
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Yusuke Tanji, Osaka, JP;

Hideki Tamura, Shiga, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02J 50/12 (2016.01); B60M 7/00 (2006.01); B60L 53/30 (2019.01); H02M 7/5387 (2007.01); B60L 53/12 (2019.01);
U.S. Cl.
CPC ...
H02J 50/12 (2016.02); B60L 53/30 (2019.02); B60M 7/00 (2013.01); B60L 53/12 (2019.02); H02M 7/5387 (2013.01); Y02T 10/7005 (2013.01); Y02T 10/7072 (2013.01); Y02T 90/12 (2013.01); Y02T 90/121 (2013.01); Y02T 90/122 (2013.01); Y02T 90/14 (2013.01);
Abstract

A control circuit is configured to adjust a phase difference which is a delay of the phase of each of the second drive signals to the phase of each of the first drive signals to a set value within a prescribed range to adjust the magnitude of output power. The control circuit includes an estimator and a setter. The estimator estimates whether an initial mode which is an operation mode of an inverter circuit in the case of a variable capacitance circuit being disabled is a leading phase mode or a lagging phase mode while the variable capacitance circuit is operating. The setter sets the prescribed range in accordance with the initial mode estimated by the estimator.


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