The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Aug. 21, 2017
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, Tokyo, JP;

Inventors:

Koh Hashimoto, Yokohama Kanagawa, JP;

Makoto Sano, Kawasaki Kanagawa, JP;

Keiju Yamada, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01Q 1/22 (2006.01); H01Q 13/10 (2006.01); H01Q 25/00 (2006.01); H01L 23/66 (2006.01); H01Q 1/38 (2006.01); H01Q 1/36 (2006.01); H01Q 1/40 (2006.01); H01Q 9/06 (2006.01); H01Q 9/26 (2006.01); H01Q 21/28 (2006.01);
U.S. Cl.
CPC ...
H01Q 1/2283 (2013.01); H01L 23/66 (2013.01); H01Q 1/36 (2013.01); H01Q 1/38 (2013.01); H01Q 1/405 (2013.01); H01Q 9/065 (2013.01); H01Q 9/26 (2013.01); H01Q 13/106 (2013.01); H01Q 21/28 (2013.01); H01Q 25/00 (2013.01); H01L 2223/6677 (2013.01);
Abstract

According to an embodiment, a wireless device includes an interposer, a semiconductor chip, and a non-conductor. The interposer comprises a plurality of conductor layers. The semiconductor chip is mounted on the interposer and comprising a built-in transceiver circuit. The non-conductor is placed on the interposer and seals the semiconductor chip. From among the plurality of conductor layers, a first conductor layer and a second conductor layer are symmetrically positioned with respect to center in a thickness direction of the interposer respectively have a first antenna conductor pattern and a second antenna conductor pattern. The first antenna conductor pattern and the second antenna conductor pattern respectively have a first opening and a second opening functioning as a slot antenna and have substantially equal area of a conductor portion. An orthogonal projection of the first opening onto the second conductor layer overlaps with the second opening.


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