The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Oct. 14, 2013
Applicant:

Cree, Inc., Durham, NC (US);

Inventors:

Sten Heikman, Goleta, CA (US);

James Ibbetson, Santa Barbara, CA (US);

Zhimin Jamie Yao, Goleta, CA (US);

Fan Zhang, Goleta, CA (US);

Matthew Donofrio, Raleigh, NC (US);

Christopher P. Hussell, Cary, NC (US);

John A. Edmond, Durham, NC (US);

Assignee:

Cree, Inc., Durham, NC (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 33/44 (2010.01); H01L 33/50 (2010.01); H01L 33/00 (2010.01); H01L 33/20 (2010.01); H01L 33/48 (2010.01);
U.S. Cl.
CPC ...
H01L 33/50 (2013.01); H01L 33/0095 (2013.01); H01L 33/44 (2013.01); H01L 33/20 (2013.01); H01L 33/486 (2013.01); H01L 2924/0002 (2013.01); H01L 2933/0041 (2013.01);
Abstract

This disclosure relates to light emitting devices and methods of manufacture thereof, including side and/or multi-surface light emitting devices. Embodiments according to the present disclosure include the use of a functional layer, which can comprise a stand-off distance with one or more portions of the light emitter to improve the functional layer's stability during further device processing. The functional layer can further comprise winged portions allowing for the coating of the lower side portions of the light emitter to further interact with emitted light and a reflective layer coating on the functional layer to further improve light extraction and light emission uniformity. Methods of manufacture including methods utilizing virtual wafer structures are also disclosed.


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