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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10439096 B1

PDFFull Text
Date of Patent:
Oct. 08, 2019

Filed:

Nov. 03, 2015

Method for manufacturing at least one optoelectronic semiconductor chip

Applicant:

Osram Opto Semiconductors Gmbh, Regensburg, DE;

Inventors:

Johannes Baur, Regensburg, DE;

Lutz Hoeppel, Alteglofsheim, DE;

Assignee:

OSRAM OPTO SEMICONDUCTORS GMBH, Regensburg, DE;

Attorney:

McDermott Will & Emery LLP

Primary Examiner:

Phuc T Dang

Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 33/40 (2010.01); H01L 33/44 (2010.01); H01L 31/02 (2006.01); H01L 31/0203 (2014.01); H01L 31/0232 (2014.01); H01L 31/18 (2006.01); H01L 33/52 (2010.01); H01L 33/62 (2010.01); H01L 33/42 (2010.01); H01L 33/46 (2010.01); H01L 33/48 (2010.01);
U.S. Cl.
CPC ...
H01L 33/005 (2013.01); H01L 31/0203 (2013.01); H01L 31/02005 (2013.01); H01L 31/02327 (2013.01); H01L 31/18 (2013.01); H01L 33/0079 (2013.01); H01L 33/0095 (2013.01); H01L 33/405 (2013.01); H01L 33/44 (2013.01); H01L 33/52 (2013.01); H01L 33/62 (2013.01); H01L 33/42 (2013.01); H01L 33/46 (2013.01); H01L 33/486 (2013.01); H01L 2933/0033 (2013.01); H01L 2933/0066 (2013.01);
Abstract

Disclosed is an optoelectronic semiconductor chip () comprising: —a succession of semiconductor layers () that has a main plane of extension, an active layer () and a bottom surface (); —a substrate () that is arranged on the bottom surface () of the succession of semiconductor layers () and has a base surface () facing away from the bottom surface (); and —a succession of joining layers () which is arranged in at least some locations between the succession of semiconductor layers () and the substrate () in a vertical direction; wherein —the substrate () laterally protrudes from the succession of semiconductor layers () by a maximum of 10 μm.

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