The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Mar. 09, 2018
Applicants:

Kabushiki Kaisha Toshiba, Minato-ku, Tokyo, JP;

Toshiba Electronic Devices & Storage Corporation, Minato-ku, Tokyo, JP;

Inventors:

Tsuyoshi Oota, Ibo Hyogo, JP;

Hiroko Nonaka, Nomi Ishikawa, JP;

Asami Gorohmaru, Himeji Hyogo, JP;

Toshiyuki Naka, Nonoichi Ishikawa, JP;

Norio Yasuhara, Kanazawa Ishikawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/74 (2006.01); H01L 29/739 (2006.01); H01L 27/02 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66348 (2013.01); H01L 27/024 (2013.01); H01L 29/0834 (2013.01); H01L 29/7396 (2013.01); H01L 29/7397 (2013.01); H01L 29/7412 (2013.01);
Abstract

According to an embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a fifth semiconductor region of the second conductivity type, a gate electrode, and a second electrode. The first semiconductor region is provided on the first electrode. The first semiconductor region includes first portions and first protruding portions. The first portions are arranged along a first direction and a second direction perpendicular to the first direction. The first protruding portions respectively protrude from the first portions. The second semiconductor regions are spaced from each other and provided in the first semiconductor region. The third semiconductor region is provided on the first semiconductor region and the second semiconductor regions.


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