The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Mar. 14, 2018
Applicant:

Asahi Kasei Microdevices Corporation, Tokyo, JP;

Inventors:

Shuntaro Fujii, Tokyo, JP;

Tatsushi Yagi, Tokyo, JP;

Shohei Hamada, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 21/266 (2006.01); H01L 29/06 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0922 (2013.01); H01L 21/266 (2013.01); H01L 21/8238 (2013.01); H01L 21/823418 (2013.01); H01L 21/823481 (2013.01); H01L 21/823493 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 27/088 (2013.01); H01L 27/092 (2013.01); H01L 27/0928 (2013.01); H01L 29/0649 (2013.01); H01L 21/823412 (2013.01);
Abstract

An object of the present invention is to provide a semiconductor device and a manufacturing method thereof that may achieve low power consumption in a digital circuit and reduce influence of noise in an analog circuit. The manufacturing method of the semiconductor device includes a first source/drain forming step of forming a first source region and a first drain region by implanting impurities of a second conductivity type into a digital side second conductivity type impurity layer using a gate electrode and a sidewall as a mask and a second drain/source forming step of forming a second source region and a second drain region by implanting impurities of the second conductivity type into an analog side second conductivity type impurity layer using a gate electrode and a sidewall as a mask more shallowly than the impurities of the second conductivity type implanted in the first source/drain forming step.


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