The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

May. 21, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Sachiyo Ito, Kawasaki, JP;

Tatsuhiro Oda, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01); H01L 21/762 (2006.01); H01L 27/11521 (2017.01); H01L 23/535 (2006.01); H01L 21/74 (2006.01); H01L 27/11568 (2017.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/743 (2013.01); H01L 21/76224 (2013.01); H01L 23/535 (2013.01); H01L 27/11521 (2013.01); H01L 27/11556 (2013.01); H01L 27/11568 (2013.01); H01L 27/11582 (2013.01);
Abstract

According to one embodiment, a semiconductor device includes a substrate, a stacked body, a plurality of columnar portions, a separation portion, and a wall portion. The separation portion extends through the stacked body in a first direction and separates the stacked body into a plurality of blocks in a second direction. The separation portion includes a conductive material contacting the substrate. The wall portion is disposed between the separation portion and a columnar portion of the plurality of columnar portions most proximal to the separation portion. The wall portion pierces a lowermost electrode layer of the plurality of electrode layers and pierces an interface between the substrate and the stacked body.


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