The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Feb. 27, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventors:

Mitsuyoshi Meguro, Yokkaichi Mie, JP;

Takafumi Ochiai, Kuwana Mie, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/683 (2006.01); H01L 21/67 (2006.01);
U.S. Cl.
CPC ...
H01L 21/6833 (2013.01); H01L 21/67063 (2013.01); H01L 21/67288 (2013.01); H01L 21/6831 (2013.01); H01L 21/6838 (2013.01);
Abstract

A semiconductor manufacturing apparatus includes an electrostatic chuck stage for configured to hold a wafer and supplying gas from a gas supply source to the wafer. The electrostatic chuck stage includes a first opening that supplies the gas to a first portion located at a first distance from the center of the wafer, and a second opening that supplies the gas to a second portion located at a second distance from the center of the wafer. The second distance being greater than the first distance. A first measurement instrument configured to measure a physical quantity of the gas between the gas supply source and the first opening, and a second measurement instrument configured to measure a physical quantity of the gas between the gas supply source and the second opening. An output device outputs information on the wafer based on the physical quantities measured by the first and second measurement instruments.


Find Patent Forward Citations

Meguro, Mitsuyoshi. (2019). Semiconductor manufacturing apparatus and wafer holding method (U.S. Patent No. 10438830). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10438830

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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