The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2019
Filed:
Mar. 06, 2018
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventor:
Donald C. Abbott, Chatley, MA (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/64 (2006.01); H01L 23/495 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4842 (2013.01); H01L 21/4821 (2013.01); H01L 21/561 (2013.01); H01L 21/64 (2013.01); H01L 23/49503 (2013.01); H01L 23/49541 (2013.01); H01L 23/49548 (2013.01); H01L 23/49575 (2013.01); H01L 24/85 (2013.01); H01L 24/97 (2013.01); H01L 23/49565 (2013.01); H01L 2224/05599 (2013.01); H01L 2224/85 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/181 (2013.01); H01L 2924/2064 (2013.01); Y10T 29/49121 (2015.01);
Abstract
In a method for fabricating semiconductor devices a leadframe pattern is formed from a flat tape of base metal. A plurality of additional metal layers is plated on the patterned tape of base metal. The surface of the metal layers is roughed. A plurality of sites for assembling semiconductor chips are created. The sites alternate with zones for connecting the leadframe pattern to molding compound runners A selected first set of leadframe areas are selectively planished creating flattened areas offsetting a second set of leadframe areas. A semiconductor chip is attached to each site.