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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10438814 B1

PDFFull Text
Date of Patent:
Oct. 08, 2019

Filed:

Dec. 15, 2017

Method for manufacturing wiring pattern, method for manufacturing transistor, and member for transfer

Applicant:

Nikon Corporation, Tokyo, JP;

Inventors:

Makoto Nakazumi, Yamato, JP;

Yasutaka Nishi, Tokyo, JP;

Kei Nara, Yokohama, JP;

Assignee:

NIKON CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:

Vu A Vu

Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/447 (2006.01); H01L 29/417 (2006.01); H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 21/4763 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 31/00 (2006.01); H01L 21/445 (2006.01);
U.S. Cl.
CPC ...
H01L 21/447 (2013.01); H01L 21/02565 (2013.01); H01L 21/02631 (2013.01); H01L 21/47635 (2013.01); H01L 29/417 (2013.01); H01L 29/4908 (2013.01); H01L 29/66969 (2013.01); H01L 29/786 (2013.01); H01L 29/7869 (2013.01); H01L 31/00 (2013.01); H01L 21/445 (2013.01);
Abstract

An object is to provide a novel method in place of the above-described conventional technology, as a technique for obtaining a thin film with a wiring pattern applied. A method for manufacturing a wiring pattern according to the present invention is characterized in that the method includes: a laminate forming step of forming a laminate by bringing a first member that has a resist layer and a metal layer formed on the resist layer into contact with a second member that includes a substrate; a resist layer patterning step of subjecting the resist layer to patterning; and an etching step of selectively removing the metal layer.

Find Patent Forward Citations

Nakazumi, Makoto. (2019). Method for manufacturing wiring pattern, method for manufacturing transistor, and member for transfer (U.S. Patent No. 10438814). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10438814

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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