The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2019
Filed:
Dec. 13, 2017
Applicant:
SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;
Inventor:
Kwi Dong Kim, Incheon, KR;
Assignee:
SK hynix Inc., Icheon-si, Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/38 (2006.01); H01L 27/115 (2017.01); G11C 29/12 (2006.01); G11C 29/48 (2006.01); H01L 21/66 (2006.01); H01L 23/544 (2006.01); H01L 27/112 (2006.01);
U.S. Cl.
CPC ...
G11C 29/38 (2013.01); G11C 29/1201 (2013.01); G11C 29/48 (2013.01); H01L 27/115 (2013.01); H01L 22/32 (2013.01); H01L 23/544 (2013.01); H01L 27/11206 (2013.01); H01L 2223/5446 (2013.01); H01L 2223/54426 (2013.01);
Abstract
A semiconductor integrated circuit device may include a plurality of semiconductor chips, a scribe lane, connecting wiring, and a selection circuit. Each of the semiconductor chips may include a peripheral circuit. The scribe lane may be positioned between the semiconductor chips. A test pad may be arranged in the scribe lane. The connecting wiring may be connected between the test pad and the peripheral circuit. The selection circuit may be configured to selectively connect or disconnect the connecting wiring.