The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2019
Filed:
Apr. 12, 2018
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventor:
Ji Hyun Seo, Seoul, KR;
Assignee:
SK hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/30 (2006.01); H01L 27/11568 (2017.01); H01L 27/11573 (2017.01); H01L 27/11582 (2017.01); G11C 16/08 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G11C 16/0466 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/30 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 27/11582 (2013.01);
Abstract
Provided herein are a memory device and a method of operating the memory device. The memory device comprises a plurality of memory cells stacked along a pillar vertical to a substrate, a peripheral circuit configured to program and verifying memory cells coupled to a selected word line, among the memory cells, and a control logic configured to control the peripheral circuit so that a pass voltage applied to unselected word lines is adjusted depending on a location of the selected word line when the memory cells are verified.