The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Jul. 24, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Ji-yoon Park, Suwon-si, KR;

Wan-dong Kim, Seoul, KR;

Seung-bum Kim, Hwaseong-si, KR;

Deok-woo Lee, Suwon-si, KR;

You-se Kim, Hwaseong-si, KR;

Se-hwan Park, Yongin-si, KR;

Jin-woo Park, Yongin-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/16 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/16 (2013.01); G11C 11/5635 (2013.01); G11C 16/0483 (2013.01); G11C 16/3445 (2013.01);
Abstract

A method of erasing a memory device, the method of erasing the memory device including: performing, in a first erase period, a first erase operation on memory cells respectively connected to a plurality of word lines, wherein at least one of the memory cells, which is included in a memory block, is not erase-passed; determining, after the first erase period, an erase operation speed by applying a verify voltage to at least one of the plurality of word lines, and determining an effective erasing time for each word line based on the determined erase operation speed; and performing, in a second erase period, a second erase operation on the memory cells respectively connected to the plurality of word lines based on the determined effective erasing times.


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