The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Nov. 27, 2017
Applicant:

SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;

Inventors:

Donggun Kim, Hwaseong-si, KR;

Jung Hyun Kwon, Seoul, KR;

Yong Ju Kim, Seoul, KR;

Do Sun Hong, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 7/10 (2006.01); G06F 12/02 (2006.01); G11C 16/08 (2006.01); G11C 13/00 (2006.01); G11C 16/34 (2006.01); G11C 7/12 (2006.01); G11C 8/08 (2006.01);
U.S. Cl.
CPC ...
G11C 11/5628 (2013.01); G06F 12/0246 (2013.01); G11C 7/1006 (2013.01); G11C 13/0023 (2013.01); G11C 13/0069 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/3427 (2013.01); G11C 7/12 (2013.01); G11C 8/08 (2013.01); G11C 11/5642 (2013.01);
Abstract

An address distribution apparatus includes an address distributor. The address distributor distributes addresses of a plurality of memory cells in a memory device to prevent at least two successive write operations from being applied to at least two adjacent memory cells sharing any one of a plurality of word lines or any one of a plurality of bit lines among the plurality of memory cells. The at least two write operations are performed in response to write requests outputted from a host, respectively.


Find Patent Forward Citations

Kim, Donggun. (2019). Apparatuses and methods of distributing addresses in memory devices for mitigating write disturbance (U.S. Patent No. 10438655). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10438655

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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