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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10438314 B1

PDFFull Text
Date of Patent:
Oct. 08, 2019

Filed:

Apr. 23, 2018

Two-pass cache tile processing for visibility testing in a tile-based architecture

Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Ziyad S. Hakura, Gilroy, CA (US);

Jerome F. Duluk, Jr., Palo Alto, CA (US);

Assignee:

NVIDIA CORPORATION, Santa Clara, CA (US);

Attorney:

Artegis Law Group, LLP

Primary Examiner:

James A Thompson

Int. Cl.
CPC ...
G06T 1/20 (2006.01); G06T 15/00 (2011.01); G06T 15/40 (2011.01); G06F 9/38 (2018.01); G06T 1/60 (2006.01); G06F 12/0875 (2016.01); G06F 9/44 (2018.01); G06T 17/20 (2006.01); G09G 5/395 (2006.01); G09G 5/00 (2006.01); G06T 15/50 (2011.01); G06F 12/0808 (2016.01); G06T 15/80 (2011.01);
U.S. Cl.
CPC ...
G06T 1/20 (2013.01); G06F 9/38 (2013.01); G06F 9/44 (2013.01); G06F 12/0808 (2013.01); G06F 12/0875 (2013.01); G06T 1/60 (2013.01); G06T 15/005 (2013.01); G06T 15/405 (2013.01); G06T 15/503 (2013.01); G06T 15/80 (2013.01); G06T 17/20 (2013.01); G09G 5/003 (2013.01); G09G 5/395 (2013.01); G06F 2212/302 (2013.01); Y02D 10/13 (2018.01);
Abstract

One embodiment of the present invention sets forth a graphics processing system. The graphics processing system includes a screen-space pipeline and a tiling unit. The screen-space pipeline is configured to perform visibility testing and fragment shading. The tiling unit is configured to determine that a first set of primitives overlaps a first cache tile. The tiling unit is also configured to first transmit the first set of primitives to the screen-space pipeline with a command configured to cause the screen-space pipeline to process the first set of primitives in a z-only mode, and then transmit the first set of primitives to the screen-space pipeline with a command configured to cause the screen-space pipeline to process the first set of primitives in a normal mode. In the z-only mode, at least some fragment shading operations are disabled in the screen-space pipeline. In the normal mode, fragment shading operations are enabled.

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