The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Dec. 16, 2016
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Vikas Chandra, Fremont, CA (US);

Mudit Bhargava, Austin, TX (US);

Assignee:

Arm Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/00 (2013.01); G06F 21/72 (2013.01); H04L 9/00 (2006.01); H04L 9/06 (2006.01); G06F 21/75 (2013.01); G06F 21/76 (2013.01); H03K 19/177 (2006.01); G09C 1/06 (2006.01);
U.S. Cl.
CPC ...
G06F 21/72 (2013.01); G06F 21/75 (2013.01); G06F 21/76 (2013.01); G09C 1/06 (2013.01); H03K 19/17768 (2013.01); H04L 9/003 (2013.01); H04L 9/06 (2013.01); G06F 2221/2123 (2013.01);
Abstract

A protected circuit includes a logic circuit having one or more input nodes and one or more output nodes. The logic circuit has a network of logic elements and one or more logic encryption elements. A logic encryption element includes a memory cell, such as a correlated electron switch for example, coupled with a configurable sub-circuit that is configured by a value stored in the memory cell to encrypt a signal or a signal path. A mapping of values at the one or more input nodes to values at the one or more output nodes corresponds to a desired mapping when values stored in the one or more memory cells match component values of a prescribed key vector. The memory cells may be programmed after fabrication of the circuit.


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