The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Nov. 28, 2017
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Alec Kochevar-Cureton, Bellevue, WA (US);

Somesh Chaturmohta, Redmond, WA (US);

Norman Lam, Sammamish, WA (US);

Sambhrama Mundkur, Sammamish, WA (US);

Daniel Firestone, Seattle, WA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 15/167 (2006.01); G06F 15/173 (2006.01); H04L 29/06 (2006.01); G06F 9/455 (2018.01); H04L 12/801 (2013.01); H04L 12/911 (2013.01); H04L 12/935 (2013.01); H04L 12/861 (2013.01); H04L 12/707 (2013.01); H04L 12/721 (2013.01); H04L 12/717 (2013.01); H04L 12/741 (2013.01); G06F 15/76 (2006.01); H04L 12/813 (2013.01); H04L 12/931 (2013.01); H04L 29/08 (2006.01);
U.S. Cl.
CPC ...
G06F 15/17331 (2013.01); G06F 9/45558 (2013.01); G06F 15/76 (2013.01); H04L 45/24 (2013.01); H04L 45/38 (2013.01); H04L 45/42 (2013.01); H04L 45/54 (2013.01); H04L 47/193 (2013.01); H04L 47/20 (2013.01); H04L 47/34 (2013.01); H04L 47/39 (2013.01); H04L 47/741 (2013.01); H04L 47/822 (2013.01); H04L 49/3027 (2013.01); H04L 49/3045 (2013.01); H04L 49/354 (2013.01); H04L 49/9068 (2013.01); H04L 69/12 (2013.01); G06F 2009/45583 (2013.01); H04L 49/70 (2013.01); H04L 67/1097 (2013.01); H04L 69/161 (2013.01);
Abstract

Distributed computing systems, devices, and associated methods of remote direct memory access ('RDMA') packet routing are disclosed herein. In one embodiment, a server includes a main processor, a network interface card ('NIC'), and a field programmable gate array (“FPGA”) operatively coupled to the main processor via the NIC. The FPGA includes an inbound processing path having an inbound packet buffer configured to receive an inbound packet from the computer network, a NIC buffer, and a multiplexer between the inbound packet buffer and the NIC, and between the NIC buffer and the NIC. The FPGA also includes an outbound processing path having an outbound action circuit having an input to receive the outbound packet from the NIC, a first output to the computer network, and a second output to the NIC buffer in the inbound processing path.


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