The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Dec. 14, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

John K. DeBrosse, Colchester, VT (US);

Daniel C. Worledge, Cortlandt Manor, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G06F 11/10 (2006.01); H03M 13/27 (2006.01); G11C 11/16 (2006.01); H01L 27/22 (2006.01); H01L 43/08 (2006.01); H04L 1/00 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1016 (2013.01); G11C 11/1677 (2013.01); H03M 13/2764 (2013.01); H01L 27/222 (2013.01); H01L 43/08 (2013.01); H04L 1/0071 (2013.01);
Abstract

A memory device, a memory system, and corresponding methods are provided. The memory device includes a non-volatile random access memory. The non-volatile memory includes a suspect bit register configured to store addresses of bits that are determined to have had errors. The non-volatile memory further includes a bad bit register configured to store addresses of bits that both (i) appeared in the suspect bit register due to a first error and (ii) are determined to have had a second error. Hence, the memory device overcomes the aforementioned intrinsic write-error-rate by identifying the bad bits so they can be fused out, thus avoiding errors during use of the non-volatile random access memory.


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