The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Jan. 25, 2018
Applicant:

Mellanox Technologies, Ltd., Yokneam, IL;

Inventors:

Ido Bourstein, Pardes Hana-Karkur, IL;

Ofer Shalev, Yokneam Illit, IL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3185 (2006.01); G06F 17/50 (2006.01); G11C 29/48 (2006.01); G06F 11/22 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318586 (2013.01); G01R 31/31858 (2013.01); G01R 31/318583 (2013.01); G06F 11/2236 (2013.01); G06F 17/5045 (2013.01); G11C 29/48 (2013.01);
Abstract

A method for circuit design includes providing one or more wrapper cells for use with a library of standard cells in design of an IC. Each wrapper cell has geometrical dimensions matching a corresponding group of one or more of the standard cells and defines an electrical path, including at least one via, from a location of a terminal in a lower metal layer in the standard cells in the corresponding group to a location in an upper metal layer. A computerized place-and-route tool receives a layout of the IC including a wrapper cell superimposed over one of the standard cells in the corresponding group. The place-and-route tool automatically routes a signal connection through the upper metal layer and the at least one via defined by the superimposed wrapper cell to the predefined signal terminal in the lower metal layer in the one of the standard cells.


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