The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2019

Filed:

Dec. 11, 2018
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Krishnan S. Rengarajan, Bengaluru, IN;

Vaibhav A. Ruparelia, Bengaluru, IN;

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/3203 (2019.01); H04L 25/03 (2006.01); H03M 7/42 (2006.01); H03K 19/177 (2006.01); H04L 27/01 (2006.01);
U.S. Cl.
CPC ...
H04L 25/03878 (2013.01); G06F 1/3203 (2013.01); H03K 19/17728 (2013.01); H03M 7/42 (2013.01); H04L 27/01 (2013.01);
Abstract

A distributed arithmetic feed forward equalizer (DAFFE) and method. The DAFFE includes look-up tables (LUTs) in offset binary format. A DA LUT stores sum of partial products values and an adjustment LUT stores adjustment values. DA LUT addresses are formed from same-position bits from all but the most significant bits (MSBs) of a set of digital words of taps and an adjustment LUT address is formed using the MSBs. Sum of partial products values and an adjustment value are acquired from the DA LUT and the adjustment LUT using the DA LUT addresses and the adjustment LUT address, respectively. Reduced complexity downstream adder(s) (which result in reduced power consumption) compute a total sum of the sum of partial products values and the adjustment value (which compensates for using the offset binary format and dropping of the MSBs when forming the DA LUT addresses) to correctly solve a DA equation.


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